number of instructions per hour to exit the pipeline.

time required between moving an instruction from one stage to the next stage.

no. of stages in pipeline

Execution time per instruction on unpipelined machine / no.of pipelinestages

IF - instruction fetch , ID - instruction decode, EXE - execution, MEM - memory access, WB - write back

increases instruction throughput, does not reduce execution time of an individual instruction, stage imbalance reduces performance: the slowest pipeline stage determines pipeline clock cycle time , overhead increases the execution time of each instruction.

Structural, Data, Control

Averageinstruction ETunpipelined / Averageinstruction ETpipelined

Ideal CPI  Pipeline stall cycles per instructio n

1

combination of instructions cannot be accommodated in one clock cycle because of resource conflicts

stall the pipeline for one clock cycle

occur when the pipeline changes the order of read/write accesses to operands.

forwarding, compiler scheduling

if forwarding hardware detects that the previous ALU operation has written the register corresponding to a source for the current ALU operation, control logic selects the forwarded result as the ALU input rather than the value read from the register file.